Like systems in every other industry, mission computers and subsystems for Defense and Aerospace (D&A) like radar, flight control, and sensor fusion are growing in complexity with a voracious appetite for computational power. However, these systems must also satisfy rigorous requirements for low weight, low power consumption, and low heat dissipation while adhering to existing form factors, backplanes, and chassis specifications.

Multi-core chips satisfy these requirements by providing significantly greater processing capacity per ounce, watt, and square inch than their uniprocessor predecessors. By extension, boards based on multi-core chips can lower the slot count and thereby reduce a system’s weight, cost, power consumption, and overall chassis size. However, it isn’t enough to get software to run on a multi-core processor — the key to success is optimizing the software to make full use of all the processor’s cores.

Download this white papaer to examine various techniques for optimizing code on multi-core processors. This white paper also addresses threading models for multiple concurrent tasks and parallel processing for increased performance.