Synplify DSP software offers hardware engineers and algorithm developers the most efficient way to implement their algorithms into FPGAs and ASICs.
Click here to learn more and download and evaluation.

The Synplify DSP architectural synthesis methodology allows designers to automatically implement and explore area/speed-optimized RTL implementations from a single model. This eliminates the burden of hand coding functions and architectural optimizations, achieves significantly faster design capture, speeds time to market and enables rapid design exploration that results in improved quality and lower cost.

The 3.6 release offers the following updates:

• New Reed-Solomon encoder and decoder functions.
• Enhanced area optimization engine can recognize repeating patterns of operations in the design and apply time-multiplexed scheduling to reduce area.
• Faster run times and better memory utilization for designs up to 35,000 blocks.
• Expanded saturation and rounding now supports six rounding modes including convergent rounding.
• Improved Divider area optimizations.
• Synplify DSP ASIC Edition includes improvements in RTL quality and new technology support for 150nm, 110nm, and 65nm technologies.
  

Click here to learn more and download and evaluation.